Automatic distribution central



Jan. 28, 1969 J. M. BIALO ETAL AUTOMAT I C DI STRIBUTION CENTRAL Filed Aug. 25, 1965 Sheet of l2 k' dZ 22 6/ 60 56 59 I 9 38 0R 57 Fup 72a 664A FLOP Z 44 MASTER' c CLOCK sclLLAraR l 2 80 634 686|. mwa 12a 242 4 6 /4251 692 699 72; 6 @ya M la 3 20e 202 fg,

72 T j y X8 79 32 232 IILHI L@ 223 224 13/ Wm N e 726 210 212 v F ""vmg '5-. 222 2/3 '48] e 53/ -rx32 2,4 21e 72j/ 62 "01 32 6 a A X64 1 72k *'58 234/ 226/ 224 26@ bug@ 237 6 4 /Zi X256 Z1 L7 l 2352215 630 .4 278 2g? ga-0J; 255'/ i L -266 INVENTORS 750 R55" 0^ gxgRglfB/EL/gm cLocK- .934 (H615 F68 TUR/v oFF REST Mam/a) BY Y AN /wa 0F C40 K @UE C GENE/Aron 668 l ATTORNEK Jan. 2s, 19695 JOHN M. BIALO EDWARD F KEISER BY g .105114 hamm A T TORNEY Jan. 28, 1969 J. M. BIALo ETAL 3,424,859

AUTOMATIC DISTRIBUTION CENTRAL Filed Aug. 2s, 1965 sheet 3 of 12 www o om v T92 :fw o 5 'l /0 /6 2a 22 t 2 6 coun-rs i INVENTORS JOHN M. a/ALo EDWARD F. frs/SER BY JOSEPH H. VOGEL NAN AT TORNEY Jan. 28, 1969 sheet 4 of12 Filed Aug. 23, 1965 5 R O T. NOC N E V m QN S S o mi SX Q @111 Il V I l I I ll Ill m S .w n S l l l i 1 l 1 l x U\ V Il K Illl QR 5x l i l i I Il u\\w Q L wx m Q QN mw NN AN Q S E Q NS m n .s4 .n v. m N Q SEQ SEP/l H. V ELHAN JOHN M. B/ALO EDWARD F- KEI TTRNEY Sheet 5 of 12 J. M. BIALO ETAL AUTOMATIC DISTRIBUTION CENTRAL Jan. 28, 1969 Filed Aug. 23,' 1965 Mmm,

Jan. 28, 1969 J. M. alALo ETAL. AUTOMATIC DISTRIBUTIQN` CENTRAL 6 of l2 Sheet iled Aug. 23, V19:55.

1511.28, 1969 J. M. :ammV ETAT. 3,424,359

AUTOMATIC DISTRIBUTION CENTRAL JOHN M. B/ALC I EDWARD E KEISER T By vasen# H-vv MWA 'A T TUR/VE Y Jan; 28, J. M. alAL ETAL. 3,424,859

AUTOMATIC DISTRIBUTION CENTRAL Sheet med Aug. 25, 1965 INVENTORS JOHN M. BIA LO EDWARD F. KEISER JGSEPH H-VOGEL'MAN ATTORNEY Jan. 28, 1969 J. M. BxA| o ETAL AUTOMATIC DISTRIBUTION CENTRAL v of l2 Sheet Filed Aug. 23, 1965 www,

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Jan. 28, 1969 Filed Aug. 23, 1965 J. M. BIALo ETAL y AUTOMATIC DISTRIBUTION CENTRAL sheet COUNT 0 T02 0 rol I '48 of l2 2 a 2 564 866 88 276 #la f) INVENTORS JOHN M. BIA LO EDWARD E KE/SER IUSEPH H. VDGELMN ATTORNEY Jan. 28, 1969 J. M. BlALo yr-:TAL 3,424,859

vAUTOMATIC DISTRIBUTION CENTRAL sheet /2 of12 Filed Aug. 23, 1965 /NVEN'TORS ./oH/v M. B/ALO EDWARD E KEISER By 10mm/LV uA/v a, d u v ATTORNEY United States Patent Office 3,424,859 Patented Jan. 28, 1969 3,424,859 AUTOMATIC DISTRIBUTION CENTRAL John M. Bialo, Jamaica, Edward F. Keiser, Syosset, and

Joseph H. Vogelman, Roslyn, N.Y., assignors to Clavier (Yorpioration, Richmond, N.Y., a corporation of New Filed Aug. 23, 1965, Ser. No. 496,734

U.S. Cl. 178-3 46 Claims Int. Cl. H041 11/20 ABSTRACT OF THE DISCLOSURE A multichannel distribution central station for teletypewriter type signals which automatically switches messages from a plurality of incoming lines to desired outgoing lines and translates the speed of all incoming messages into one or more desired standard outgoing message speeds.

This invention relates to communication systems and particularly to a multichannel distribution central station for teletypewriter signal systems.

Teletypewriters transmitting at conventional speeds of 75 to 150 words per minute are still in use but are becoming obsolete and are being supplanted by faster teletypewriters capable of handling speeds up to 1200 words per minute and data transmitters capable of handling up to 1200 bits per second. As these improved equipments are developed and introduced into tactical field communication networks, there is a simultaneous need for high speed switching and speed translation equipment which can make the newer equipments compatible with existing communication devices.

While speed translation of Teletype Baudot code or Fieldata bits can be readily accomplished by using large data handling equipments and computers, these complex and giant xed station computers obviously become impractical for tactical eld communications.

It is an object of the invention to provide an improved distribution central station for a communication system which receives messages at various speeds on a plurality of incoming lines and switches them to desired outgoing lines with a carbon copy of selected incoming messages to a selected outgoing line.

It is also an object of the invention to provide an improved distribution central station which receives messages at various speeds on a plurality of incoming lines and automatically translates them to one or more standard speeds for transmission on outgoing lines.

It is further an object of the invention to provide an improved distribution central station which is small in size, light in weight and portable for field application such as military duty.

In accordance with this invention there is provided an automatic multichannel distribution central station which comprises a plurality of incoming message lines adapted to receive a message having informational bit pulses and address bit pulses, a plurality of outgoing message lines and channel equipment associated with each of the incoming message lines; the channel equipment comprising a master clock oscillator; a first means coupled to its associated incoming line and the master clock oscillator for detecting the bit pulse rate of a message appearing on its associated incoming message line; a second means coupled to the first means for generating a signal corresponding to the bit pulse rate of the message detected by the first means; a shift register; a third means coupling its associated incoming line and the second means to the shift register for selectively transferring the informational bit pulses from its associated incoming message line into the shift register; a message storage means; a fourth means coupling the shift register to the message storage means for selectively transferring a group of the informational bit pulses from the shift register into and to fill the message storage means; a fifth means for determining when the message storage means is filled with the groups of the informational bit pulses; a sixth means coupled to the shift register for storing the address bit pulses conf taining intelligence as to which outgoing line is to receive the informational bit pulses appearing on its associated incoming line; a seventh means coupled to the sixth means for determining -whether the outgoing line corresponding to the address bit pulses is available; an eighth means controlled by the lifth and seventh means and coupling the message storage means to the shift register for dumping the groups of informational bit pulses from the message storage means back into the shift register when the outgoing line corresponding to the address bit pulses is available; and a ninth means coupling the' shift register to the outgoing message line corresponding to the address bit pulses.

Overall circuit simplification is achieved and equipment bulk is reduced by:

(A) Switching (rather than duplicating) components within each channel equipment where there is need for the same circuits to transfer (dump) the stored message bits out of the memory system as was needed to transfer (fill) the incoming message bits into the memory system. Examples of such component circuits are: counter chain frequency dividers, clock reset generator, bit counter, character counter, early and late gate generators and shift register;

(B) Utilizing components in common (rather than duplicating) among all channels. Examples of such components are: master clock oscillator, channel access encoder, carbon copy line selector and outgoing line availability/unavailability detectors; and

(C) Time Sharing (rather than duplicating) components among all channels. Examples of such components are: input circuitry (data input funnel) 4to memory or message storage system, word location funnel for memory system, load/unload funnel for memory system, output circuitry (data output funnel) from memory system and addressed output line selector.

In one embodiment of the invention, Fieldata and Baudot coded messages at various input speeds are temporarily stored in a magnetic core memory and are then retransmitted at standardized output speeds to accommodate available receivers. Accordingly, transmitters and receivers which operate at different speeds become compatible. A particular advantageous embodiment of the invention handles eight input lines and eight output lines and automatically identilies and adapts itself to 75, 100, 150, 600 or 1200 words per minute Baudot code, or to 75, 150, 300, 600 or -1200 bits per second Fieldata. For simplification and standardization purposes, previously developed NAND logic modules will be used throughout the system. A single central clock provides a common time base for all channels of the system. The complete system can advantageously be encased in four cabinets of identical shape and size for providing portability in the eld.

As contemplated, upon accepting incoming messages, the transmission speed is detected so that sensing intervals may be established during which the subsequent bits making up the characters can be read and identified. This detection is accomplished by measurement of the time interval between the first and second transitions of the first prefatory character of the message.

The message input signal, reconstituted by a Schmitt trigger, is applied to a signal gate which passes it, unless blocked, by an inhibit voltage (present only when the previous message has not yet been cleared). The rst two transitions, whether positiveor negative-going, generate a pair of pulses, the spacing between which is used by the speed-recognition logic to ascertain the message speed.

The first transition of the lirst pulse starts a counter chain network which establishes a series of gates, each occurring at specific intervals and for specific periods after the starting pulse. Occurrence of the second transition of thefirst pulse during one of these gate periods provides an indication of message transmission speed and a corresponding identifying signal is generated. lf the second transition of the first pulse does not occur during one of these gate periods (due to either its occurrence between periods or non-occurrence during the full counting interval) a Non-member signal is generated instead.

The counter chain is made to serve a dual function, being employed not only for the initial interval measurement but also for the establishment of synchronized gates at which the signal is subsequently sensed to determine presence or absence of pulses. Since a separate counter chain is needed for each of the eight input signal channels, it therefore becomes important that the number of components, and hence the number of clock counts, be minimized. Selection of as slow a clock frequency as possible, while stillproviding the required resolution, is important in reducing the size and complexity of the computer. It has been found that a rate of 171.84 kilopulses per second is particularly advantageous from considerations of the nominal bit-intervals of the various transmission speeds of input signals, the tolerances thereon, the guard band requirements and the necessary integral relationships inherent in lthe counting network output. The numbers of clock counts corresponding to the various transmission speeds are indicated at the ip-ops following the counter chain networks. In association with these gates there is provided lock-forward circuitry to prevent subsequent recurrence of a gate while permitting relatively simple gate generators. For example, the 8-to-l0 count gate for 1200 bits per second Fieldata would also occur at 24-to- 26 counts, 264-to-266 counts, etc. without such feature.

Occurrence of the second transition of the rst pulse within one of the gate periods thus established causes the flip-flop lassociated with the particular kind and speed of transmission represented by that gate to enter the set condition. This permits processing of the remainder of the message, the detection function ceasing to be operative. Should the second transition occur during a period when no gate is open, a non-member condition is invoked; should no second transition occur at all before a selected long count, of say 424, the leading edge of a 424-to-432-count generator is employed to create the non-member condition.

Once a specific type and speed of transmission has been detected as indicated by the associated flip-flop entering the set condition, synchronization, i.e., the establishment of a series of properly timed gates during which each subsequent bit is looked at, takes place. The manner in which synchronization is accomplished for Baudot and for Fieldata transmission differs somewhat because of certain inherent differences in these codes. Baudot transmission which is used mostly for teleprinter communications, is fundamentally non-return-tozero between bits and the message may furthermore pause at the end of any character, resuming again only after an indeterminate period. Fieldata transmission, on the other hand, proceeds without interruption once started, and is not only inherently return-to-zero between bits but may have a duty cycle as small as 20%. Basically, for' both Fieldata and Baudot codes, synchronizing intervals are employed each separated in time by the nominal interval between bits in the message. Also, for Baudot ltransmission the count is restarted from the first bit of each character while for Fieldata the count is restarted by the nominal bit period 4 if the signal is a ZERO (0) or after each ONE (l) as it occurs in the message.

For Fieldata, the leading edge of the ONE 1) pulse resets a counter to zero a-nd a counter, which is similar to the detection counter then generates an interval N which is substantially 10% of a nominal period between bits, at the end of which a shift register is pulsed.

In the event that one of the ZEROs in a Fieldata message is replaced by a synchronizing pulse the counter is resynchronized by its leading edge, the same as was done in the case of a ONE in the Fieldata message. Subsequent readings will then be correspondingly closer to mid-pulse position, permitting even greater variation in speed. Greater positive variations in speed are also permitted for duty cycles greater than 20%.

In addition, an early zone gate, of width equal to that of gate N, preceding the expected time of arrival of the first transition is provided. Noise pulses arriving outside'of the looking period are gated out.

For Baudot signals, the initial synchronization is effected by the leading edge of the initial character pulse, with which each Baudot character always starts, and the bits subsequently are read into a shift register, in the same manner as used for Fieldata. VReading takes place near the mid-pulse position, the gating being quite analogous to that occurring in an ordinary mechanical teleprinter. Since the spacing between Baudot characters is variable, synchronization also starts anew with each character. Because of the shorter character bit-length and the virtually duty cycle of Baudot transmission, it is possible to use much wider gates than for Fieldata, and hence accommodate manifold greater transmission speed variations than can be tolerated for Fieldata. transmissions.

To minimize the number of components, the same register is used for both Baudot and Fieldata messages and for the same message going into and out of the memory system. Advantageously, the register has a capacity of 8bits, all of which are transferred in parallel to Vspecific addresses in the core memory, at S-bit intervals.

The lling of the memory proceeds until all the cores allocated to the channel in question have been placed in the required states, then the cycle is repeated. The input message has two prefatory characters (one for speed and type of transmission detection and one for address information) which are to |be stripped fromthe outgoing message. Since the system is designed for fixed length messages, this is readily accomplished by making the input message two characters longer than the capacity of the memory. The rst two characters are thus destroyed when printed over by the last two.

Auxiliary counters are provided' which automatically transfer the memory from its fill toits dump rnode when the fixed length message has been completed. Switching to the appropriate output line or lines is automatically accomplished by gates which are triggered `by the content of the second prefatory character of the message. This character contains tlhe routing information, which may |be to any one of the eight output lines, either with or Iwithout a carbon copy to a predetermined one of them, as designated by the setting of a manual selector switch. For Baudot input messages, the output message can advantageously be 100 Iwords per minute, 7.5-unit Baudot and for all Fieldata input messages the output message can Ibe 600 b.p.s. Fieldata, 50% duty cycle.

A busy condition of the output line designated (or of the line for which a carbon copy is designated) or other condition preventing acceptance of input messages is indicated by a clhange in input line impedance.

Other objects and features of the present invention will be set forth or apparent in the following description and claims yand illustrated in the accompanying drawings, which disclose rby way of example and not by Way of limitation, in a limited number of embodiments, the

principle of the invention and circuit implementations of the inventive concept.

In the drawings, in which like reference numbers designate like components in the several views:

FIGS. la and 1b illustrate a portion of ya single channel of the multichannel automatic distribution central station according to the invention and in particular circuitry for identifying the transmission speed of a message received by such single channel;

FIG. 2 illustrates a typical eight bit character of a message in Fieldata code;

FIG. 3 illustrates a typical eight bit character of a message in Baudot corde;

FIG. 4 represents pulses generated in the system of FIG. 1a which identify the speed of the Fieldata message illustrated in FIG. 2;

FIG. 5 represents pulses generated in the system of FIG. 1a which identify the speed of the Baudot message illustrated in FIG. 3;

FIG. 6 illustrates the gate intervals generated in the selective portion of FIG. 1a which identify three diierent incoming message speeds;

FIG. 7 illustrates the generation of a gating interval in FIG. 1a to identify a single transmission message speed arriving on an incoming line of FIG. la;

FIG. 8 represents another portion of the automatic distribution central station system which is to be considered with FIGS. 1a and lb, FIG. 8 particularly illustrating, according to the invention, the routing of incoming messages into a memory system, out of the memory system and onto a desired outgoing message line, with a carbon copy to another desired outgoing line;

FIG. 9 illustrates the system according to the invention for automatically routing a message out of the memory system and onto a desired outgoing line with a carbon copy to another selected outgoing line;

FIG. 10 illustrates a word locator funnel for the memory system illustrated in FIG. 8 according to the invention;

FIG. l1 represents a load/unload funnel for the memory system of FIG. 8 according to the invention;

FIG. 12 represents a data input funnel for tbe memory system illustrated in FIG. 8 according to the invention;

FIG. 13 represents a data output funnel according to the invention for the memory system illustrated in FIG. 8;

FIG. 14 illustrates the establishment of early gates for Fieldata and the late -gates to generate shift pulses and to synchronize the resetting of the counter chain network of FIG. la according to the invention;

FIG. l5 illustrates the establishment of early gates for Baudot messages to synchronize the resetting of the counter chain network of FIG. la according to the invention; and

FIG. 16 illustrates an Outgoing Line Request Funnel for idetenmining, on a line sharing basis, whether the `desired outgoing line is available with or without simultaneous transmission of a carbon copy of the message.

FIGS. la, lb and 8 represent one channel of a multichannel automatic distribution central station which is connected at its input side to a plurality of incoming message lines 10 (FIG. la) and at its output side to a plurality of outgoing message lines 12- (FIG. 8). For illustration only, eight incoming lines 10a to 10h and eight outgoing lines 12a to f12h will be assumed. The messages on lines 10a to 10h can either appear in Baudot code or Field-ata code, either code occurring at any one of a number of message speeds. For instance, the Baudot code could be at either 75, 100, 150, 600 or 1200 words per minute and the Fieldata message speed could be either 75, 150, 300, 600 or 1200 bits per second. 'Ilhe automatic distribution central station channel of FIGS. la, 1b and 8 switches the message on any incoming line 10, such as 10a, to a selected one, such as 12b, of a plurality of output message lines 12 with a carbon copy, if desired, of such outgoing message on another preselected output message line, such as 12a. Furthermore, the automatic distribution central station translates the message speed on incoming lines 10 so that the message speed on the outgoing message lines 12 are all at a selected standard message speed. For instance, regardless of the messages speed of the Baudot code on line 10a, a single standard Baudot code fwould appear on one of the output lines y12a to 12h at 100 words per minute and any Fieldata code appearing on line .10a will be translated to 600 bits per second on the selected one of the output message lines 12a to 12h.

In FIG. la, incoming message line 10a is connected to a Schmitt trigger 14 which regenenates the coded signal on line 10a so as to eliminate noise and reshape the incoming signal. A NAND gate 16 has one input connected by a lead 18 to the output side of Schmitt trigger .14. The other input to NAND gate 16 on line 20 opens the gate 16 when the channel is not in a dump mode and the control of the signal on line 20 will be explained later. At this time, it will be assumed that gate 16 is open and the message signal on the output lead 22 of gate 16 is conducted to the input sides of a delay multivibrator 24 and an inverter 26. The output of inverter 26 is connected to the input side of another delay multivibrator 28 by a lead 30.

FIG. 2 represents an incoming message 0,0,1,l,0,0,l,1 in Fieldata code. FIG. 3 represents the same message in Baudot code. It will be assumed that each input message has two prefactory characters (one to be used for detection of message speed along with type of transmission and one containing Outgoing line address information) which are later stripped Vfrom the output message. From FIGS. 2 and 3, it will be clear that the incoming message speed can be identied by the time interval between a to b of FIG. 2 (Fieldata code) or a to b of FIG. 3 (Baudot code).

Multivibrators 24 land 28 are single-shot multivibrators which produce a single pulse of a preselected pulse width when energized at their input sides with a positive going transition. Accordingly, the signals at the output sides of multivibrators 24 and 28 on lines 32 and 34 are shown in FIGS. 4 and 5 as c and d (Fieldata code) or c' and d (Baudot code). The time interval between pulses c and d or c' and d establishes the message speed. The inverter 26 is necessary since we are interested in both the first positive and the first negative transition of the rst pulse of FIG. 2 or FIG. 3 and multivibrators 24 and 28 respond to transitions in the same direction.

A pair of NAND gates 36, 38 each has one input connected to lines 32 and 34, respectively. The other inputs to gates 36 and 38 are inhibiting inputs connected to a lead 40 to prevent message transmission through the automatic distribution station for a short period, say 200 microseconds, at the beginning of the message storage or fill mode (to be explained later). The output of gates 36 and 38 on separate leads 42 and 44 are connected t0 an OR gate 46 which places the signals onto lines 42 and 44 to a single output lead 48 in an inverted relationship. Lead 48 is connected to one input of a NAND gate 50. At the time when the rst pulse appears on lead 48, the other two inputs on leads 52 and 54 respectively have signals thereon (as explained later) to open gate 50 so that the iirst pulse corresponding to c or c of FIGS. 4 or 5 on lead 48 is conducted to one input of OR gate 56 by a lead 58. The signal on lead 58 is the start of sequence signal to open NAND gate 60 for allowing the output of master clock oscillator 62 (which is constantly running and common to all channels) on lead 64 to enter counter chain network 66 on lead 68 connected to the output side of gate 60. The frequency of clock oscillator 62 is substantially greater than the highest bit rate interval of the Fieldata message code and we will assume that the frequency of oscillator 62 is 171.85 kps.

7 The start of sequence pulse on lead 58 (corresponding to c or c of FIG. 4 or FIG. 5) is conducted through gate 56 to a lead S7 which is connected to the set terminal 59 of a flip-flop 61 to provide an enabling signal on its output lead 63 to gate 60 for opening the latter.

Counter chain network 66 comprises a plurality of serially connected dividers, each dividing the frequency at its input side by two. In the embodiment shown in FIG. la, twelve dividers 72a, 72b, to 72m are connected in series to lead 68. The signal on output lead 74 of frequency divider 72d has divided the frequency of oscillator 62 lby a factor of .16 and, for the embodiment illustrated, the period of the signal on line 74 is chosen to be 93 microseconds. Such frequency (10.74 kps.) will hence forth be designated as count l. Accordingly, the output frequency of dividers 72e, 72f, 72g, to 72m will be count 2, count 4, count 8 to count 256, respectively.

Each of the dividers 72a to 72m have a second output terminal (illustrated at the right hand sides thereof in FIG. la) for providing an inverted polarity signal which is 180 out of phase with the signal on the serial signal path between the frequency dividers. As shown, frequency dividers 721 and 72g have such inverted outputs n terminals 76 and 78 respectively, the signal on Vsuch terminals being designated and 8 as meaning inverted 4 and inverted 8, respectively. Hencefoith, corresponding symbolism will have corresponding meaning in this disclosure.

FIG. 6 illustrates the occurrence in point of time of pulses d or d (FIGS. 4 or 5) for 1200 Fieldata, 600 Fieldata and 1200 Baudot code as dashed lines 80, 82 and 84, respectively, with reference to time equal zero when the first pulse c or c (FIG. 4 or FIG. 5) appears on lines 48, 58 and 68. An assumption will now be made that a message appears on the incoming line 10a in 600 Fieldata code and the circuitry for identifying such code will now be described. As previously stated, pulse d (second transition of first prefactory character) appears on lead 42 and a 600 Fieldata code would space pulse d from pulse c (first transition of first prefactory character) by an interval of 18 time counts. Lead 42 is connected to the input side of an inverter 86 and a lead 88 is connected between the output side of inverter 86 and one input side of a NAND gate 90. Assuming an enabling signal on the other input lead 92 (to be explained later) to gate 90, the signal on the output lead 94 of gate 90 will have impressed thereon pulse d of FIG. 4. Lead 94 is connected to the set input terminal of each ip-ops 96, 98, 100, 102 and 104 (see FIG. lb), the resulting output of such flip-flops representing 1200, 600, 300, 150 and 75 Fieldata codes on output leads 108, 110, 112, 113 and 116, respectively. The enabling input terminals 118, 120, 122, 124 and 126 of liip-ops 96, 98, 100, 102 and 104 are connected to leads 130, 132, 134, .136 and 138 respectively.

Counter chain network 66 also comprises a plunality of NAND gates shown in FIG. la -as 142a to 142p (fifteen in number in accordance with the assumptions made for illustrative purposes only). Inputs to such NAND gates have symbolism to denote connections to the frequency dividers 72a to 72m as explained above. For instance, NAND gate 14211 has 3 signal inputs 16, 8 and from frequency dividers 72h, 72g and 72f by lead connections 144, 146 and 148 to the serial output of divider 72h, inverted terminal 78 and inverted terminal 76, respectively.

Referring to FIG. 7, wave form A represents the serial output of frequency divider 72d on lead 74 as a count l frequency. Wave forms B, C, D and E represents the outputs of 72e (count 2), 72]C (count 4), 72g (count 8) and 72h (count 16), respectively. Since gate 14211 is a NAND gate, each of the three frequency divider signal inputs and also the signal on lead 131 must be a l for impressing a signal on output lead 132 from 14211. FIG. 7 shows the inverted wave and 8 of C and D as dashed lines F and G. Inspecting FIG. 7, it is found that the conditions for opening Igate 14211 appear only during the count interval 16 to 20 in respect of wave forms '8 and 16, and when the signal on lead 131 is a 1 (to be explained later). The bottom wave form on IFIG. 7 duplicates the gate diagram of FIG. 6 with respect to 600 Fieldata code which hfas a bit frequency rate represented by the dashed line 82. Accordingly, the signal on lead 132 enables ipop 98 for the interval count 16 to count 20 to permit the d signal (FIG. 4) on lead 94 to provide a distinctive signal on lead to announce that the message code on incoming line 10a is in 600 Fieldata code. It is to be understood that all of the signal input connections between NAND Igates 142a to 142p and frequency dividers 72a to 72m will be made according to the symbolism shown in the example given. Therefore, distinctive signals on leads 116, 114, 112, 110 and 108 (FIG. 1b) represent the identiication of the incoming message on line 10a as 75 Fieldata, Fieldata, 300 Fieldata, 600 Fieldata and 1200 Fieldata codes, respectively.

Similarly, a plurality of flip-flops, shown in FIG. 1b as five flip-flops 150, 152, 154, 156 and 158, each have their enabling inputs connected to leads 160, 162, 164, 166 and 168, respectively. Further, each of such flip-flops have their set input terminals connected to lead 94. Lead 160 is connected to the outputs of gates 142:1 and 142b and according to the connections shown in FIG. la, a gating interval of 352 to 416 counts will appear thereon. Lead 162 is connected to the output of gate 142e and a gating interval of 256 to 320 counts will be impressed thereon. Lead 164 is connected to the outputs of both gates 142d and 142e for generating thereon a gating interval of 176 to 208 counts. Lead 166 is 'connected to the outputs of gates 142k to 142i which generate gating intervals of 44 to 52 counts. Lead 168 is connected to the outputs of gates 142k and 142m, for generating a gating interval of 22 to 26 counts. In this manner, distinctive signals will be generated in FIG. lb at the output sides of flip-Hops 150, 152, 15'4, 156 and 158 on leads 170, 172, 174, 176 and 178 to identify a message signal on incoming line 10a as 75 Baudot, 100 Baudot, 150 Baudot, 600 Baudot or 1200 Ba-udot, respectively.

Unless some lock out circuitry is incorporated in the counter chain network 66, the gating interval 143 in FIG. 7 of 16 to 20 will repeat lbetween count intervals 48 to 52 and 80 to 84, etc., each separated by 32 counts. Since it is important to eliminate all but the first gating interval (such as 16 to 20 on line 132), FIG. la shows counter chain network 66 as incorporating a plurality of NAND gates 182, 186, 190, 194', 198, 202, 206, 210, and 214 which are each connected at its input side in a feedback loop from the next lower frequency tiip-iiop of the group 96 to 104 and 150 to 158. For example, lead 110 which identifies 600 Fieldata code is connected to one input of gate 214 which is associated with the gate 1420 of the next higher message code frequency. Gate 214 iat its output side is connected to the input of a gate 216 by a lead 218 and the output of gate 216 is connected to one input of gate 1420 by a lead 220. Another input of gate 214 is connected to the E output of flip-flop 72h according to the symbolism explained. Another input of gate 214 is connected to the output of a gate 212 `by a lead 222, the latter gate being connected to the output of gate 210 Eby a lead 224. Also, the output of gate 212 is connected to lead 131 which is connected to one input of gate 142n as previously explained. One of the inputs to gate 210 is connected fto lead 178 of tiip-flop 158 (which is the next lower message frequen'cy identifier) by a lead 226. Another input of gate 210 is connected to the output of a gate 208 by a lead 228 which is also connected to a lead 230 connected to one input of both gates 142k and 142m. The input of gate 208 is connected to the output of gate 206 by a lead 232 while one of the inputs to gate 206 is connected tto the lead 112 (which is connected to flip-ilop 100 of the next lower frequency) by a lead 234. In similar fashion, one input of gates 182, 186, 190, 194, 198 and 202 is connected to leads 170, 172, 174, 116, 114, and 176, respectively. Also, the outputs of :gates 182, 186, 190, 19M, 198 and 202 are connected to the inputs of igates 184, 188, 192, 196, 200 and 204 by leads 236, 238, 240, 242, 244 and 246, respectively. Further, the output of gate 184 is connected to both an input of gate 186 and one input of gate 142e by a lead 248, the output of gate 188 is connected to an input of gate 190, an input of gate 142d and an input of gate 142e by a lead 250, the output of gate 192 is connected to an input of gate 1427'l and an input of gate 194-lby a lead 252, the output of gate 196 is connected to an input of gate 142g and an input of gate 198- by a lead 254, the output of gate 200 is connected to an input of gate 202, an input of igate 142k and \an input of gate 142i is connected by a lead 256, and the output of gate 204 is connected to an input of gate 142i and an input of gate 202 by a lead 258.

The lock-out circuit functions as follows. The first gating pulse between the intervals 16 and 20 appearing on line 110 causes a distinctive signal 0 to appear on lead 110 and since the signal on the other inputs to gate 214 on leads 222 and 1 6 are also the same distinctive signal 0, the signal on the output 218 of NAND gate 214 is a 1. Accordingly, the signal on the output lead 220 of inverter 216 `is a and gate 1420 together with its Hip-llop 96 is locked out. All the other message codes which have a slower frequency than the 600 Fieldata code are automatically locked out because their bit pulses occur later in time than the bit pulse frequency rate of the 600 Fieldata code.

Since spurious responses can normally be expected on lead 132 at counts 48 to 52, 8O to 84, 112 to 126, 144 to 148, 176 to 180, 208 to 212, etc., all occurring 32 counts later, 64 counts later, 128 counts later and 256 counts later, each of such spurious responses, in order, are locked out by gate 198 (and inverter 200), gate 194 (and inverter 196), gate 190 (and inverter 192) and gate 186 (and inverter 188). When any of the spurious responses tend to occur at 32 counts, 64 counts, 128 counts and 256 counts, the potential on lead 228 becomes 0 to close NAND gate 210. Thereby a 1 signal is impressed on lead 244 which because 0f inverter 212 impresses a 0 signal on lead 131 to close NAND gate 142n for preventing such spurious responses on lead 132.

By the arrangement just described, lock-out circuits including gates 182 to 216 assure that each of the leads 130 to 138 and 160 to 168 and 260 have but a single detection gating interval without other spurious responses.

Leads 170, 172, 174, 176, 178 (FIG. 1b) are connected to respective inputs of a NAND gate 262, the latter being connected to leads 92 and 54 through an inverter 264 and a lead 26S. A lead 266 connected to the intrconnection between gates 262 and 264 has a distinctive signal impressed thereon only when the incoming message on line is in Baudot code.

Leads 108, 110, 112, 114 and 116 are connected to respective inputs of a NAND gate 268. The output of gate 268 is connected to leads 92 and 54 through an inverter 270 and lead 26S. A lead 272 connected to the interconnection between gates 268 and 270 will have a distinctive signal impressed thereon when incoming line 10 detects a message in any Fieldata code.

Accordingly, Whenever any member code (75 Baudot, 100 Baudot, 150 Baudot, 600 Baudot, 1200` Baudot, 75 Fieldata, 150 Fieldata, 300 Fieldata, 600 Fieldata, or 1200 Fieldata) appears on incoming line 10a, the signal generated on leads 265, 92 and 54 closes gates 90 and 56 to signify that the initial detection was accomplished for the purpose to be explained hereinlater.

As shown in the circuits in FIG. 1a, it is preferable to start and stop the master oscillator signals on lead 68 at the beginning and end of each character of a Baudot code. That is to say, referring to FIG. 3, the timing signals on lead 68 are to start when the transition a occurs and such signals are to stop after 7.42 bits (of after the eighth bit). Accordingly, an OR gate 274 has one input connected to a lead 276 which is connected to a circuit (to be explained later) which yields a 1 signal whenever eight bits of Baudot code are counted. The output of gate 274 is connected to the reset terminal of ip-op 61 by a lead 278 so that a signal appearing on lead 276 at the end of each Baudot character will reset ip-tiop `61 to close gate 60 and thereby prevent the output of master clock oscillator 62 from reaching lead 68.

On the other hand, the master clock oscillator signals are maintained uninterrupted on lead 68 throughout a Fieldata message transmission or during an eight bit character in Baudot code but flip-flops 72a to 72m are reset at a time interval of one bit rate for both codes. The reset signal is conducted by a lead 277 connected to all the reset terminals of flip-flops 72a to 72m, lead 277 being connected to the output side of a delay multivibrator 278 which forms a required reset pulse whenever any one of its six inputs are properly energized. One of the inputs to 278 is connected to lead 63 which has a reset positive transition generated thereon whenever f'lip-op 61 turns off clock gate 61, as for instance at the end of each Baudot character. Another input to 278 is connected to the output side of a delay multivibrator 280 by a lead 282. The input side of 280 is connected to lead 265 which has a distinctive signal impressed thereon whenever a message appears in either Fieldata or Baudot code as determined by flip-flop 150 to 158 and 96 to 104. Accordingly, a reset signal appears on lead 277 whenever an initial detection is accomplished.

Preferably, according to the invention, the outgoing messages on lines 12a to 12h are either 600 Fieldata code or words per minute Baudot code. That is to say, a message on incoming line 10a in either 75 Fieldata, 150 Fieldata, 300 Fieldata, 600 Fieldata, or 1200 Fieldata code will be translated upon one of the output lines 12a to 12h according to the coding in the second prefatory character but always at -an outgoing 600 Fieldata code. Also, any message upon incoming line 10a in 75 Baudot, 100 Baudot, 150 Baudot, 600 B-audot, 1200 Baudot, will be translated and appear on one of the output lines 12a to 12h according to the coding in the second prefatory character but at a speed of 100 words per minute. Accordingly, in order to set the selected standard Baudot and Fieldata outgoing message speeds, counter chain network 66 incorpor-ates NAND gates 284 and 286, one input of gate 284 'being connected to lead 266 (the Baudot code identifying output) and one input of gate 286 being connected to lead 272 (the Fieldata identifying output). Another input of both gates 284 and 286 is connected to a lead 287 upon which is impressed a signal to signify the beginning of the dump mode which will be explained later. The other tive inputs to gate 284 are connected to the 128, 84, E and 16 terminal outputs of flip-Hops 72k, 72]', 721' and 72h, respectively. The other four input terminals of gate 286 are connected to the 8, 2t, 2 and 1 output terminals of flip-flops 72g, 72j, 72e and 72d, respectively. A common lead 285 is connected to the output sides of both gates 284 and 286. With such circuit connections, standard pulse signals synchronized to 600 Fieldata and 100 Baudot bit rates (only) will be generated on lead 285.

The circuitry described hereinbefore automatically identities the type of code and speed of the incoming message on line 10a. The routing of the message as well as the translation of the message speed to a standard output message speed will now be described.

The incoming message signals on line 10a appear on lines 22 and 30 of FIG. la and such leads are connected to the input side of a shift register 288a. such Ias Model No. SR-3O as manufactured by Computer Control Co., Inc., Framingham, Massachusetts. As shown in FIG. 8,

shift register 28811 has iiip-tiops 29011, 29211, 29411, 29611, 29811, 30011, 30211 and 30411, one for each of the eight bits making up a single character. When a lead 306 connected to all the shift pulse input terminals of flip-flops 29011 to 30411 has impressed thereon the shift signals corresponding to the incoming bit rate, each message character appearing on incoming line 1011 will be shifted into the register 28811. That is to say, if the incoming signal is coded as that shown in FIGS. 2 or 3, the first bit signal appearing on lines 22 and 30 is shifted into iiip-op 30411 upon the occurrence of the first shift pulse. When the second bit pulse of 0 appears on lines 22 and 30, the first 0 in flip-op 30411 is shifted to 302 while the second 0 signal is shifted into flip-iiop 30211. Upon the occurrence of the third bit signal of 1, it is shifted into iiip-iiop 30411 while the 0 signal in flip-fiop 30411 is shifted to flip-fiop 30211 and the 0 signal in 32211 is shifted into flip-flop 300a. Accordingly, with the incoming signal on line 1011 shown in FIG. 2 or 3, the bit signals will appear in register 28811 after eight shift pulses as 0, 0, 1, 1, 0, 0, 1, 1 in flipiiops 29011, 29211, 29411 29611, 29811, 30011, 30211 and 30411 as shown in FIG. 8. For generating the shift pulses on lead 306, a delay multivibrator 310 is connected at its input side to a lead 312 on which is generated signals a predetermined time interval after the nominal or expected time when a message bit arrives or is expected (to be explained later in reference to FIG. 14), delay multivibrator 310 responding only to positive going transitions and providing pulses of a preselected width. Accordingly, if the incoming message on line 1011 is in 600 Fieldata having a nominal bit rate of 18 counts, a negative transition occurs on lead 312 at count 16 while a positive transition occurs at count 20. Therefore, delay multivibrator 310 will produce a shift pulse at count 20 on its output lead 314, such pulse occurring at count 20 to avoid the transition at count 18 and also so that the nominal 600 Fieldata pulse occurring at count 18 even if slightly delayed (by two counts) will still be shifted into register 28811. If the incoming message on line a is 150 Baudot, a shift pulse is delayed by 64 counts after the nominal bit rate of 96 counts to avoid the transitions at 0 and 96 counts. A power amplifier 316 and an OR gate 317 are connected between the output of delay multivibrator 310 and lead 306.

After one character or eight bits of the incoming message on line 1011 is shifted into register 28811, it is stored in a memory system 320 such as Model No. 1024 MSRS of the random access type as manufactured and supplied by Indiana General Corp., Keasbey, N J. For the embodiment illustrated, memory system 320 has 1024 memory cores divided into eight sections or channels 322, 324, 326, 328, 330, 332, 334 and 336. As shown in FIG. 8, a data electronic commutator 338 (to be described later) is connected at its input side to the eight shift registers (similar to 28811) -associated with the eight incoming lines (1011 to 10h), FIG. 8 merely showing the connections to one shift register 28811. The signals from all eight shift registers appear on leads 34011 to 340k between data electronic commutator 338 and memory system 320 on a time sharing basis, for instance, each shift register is sequentially connected to memory system 320 for 1/s of a count. The interrupted or commutated bits on lead 34011 which correspond to the message on the incoming rnessage line 1011 all must be routed to one particular memory section 322 to 336 so that each of such memory sections or channels contains the full message on one of the incoming lines 1011 to 10h even though, obviously, the bits of one message do not occur uninterruptedly on line 34011. However, the message bit information which is stor'ed in any one of the sections 322 to 336 is sequentially positioned therein.

After any one of the memory sections 322 to 336 is filled (for instance, after 128 informational characters plus two prefatory characters appear on its associated incoming line 1011 or 10h), 128 informational characters can be dumped on Iany one of the preselected outgoing lines 1211 to 12h with carbon copy to another line (if both are available or not used) according to the coding of the second prefatory character in any message. Any one or any number of the memory sections 322 to 336 can be dumping on memory system output leads 34211 to 34211 at the same time while the other sections can be filling on memory system input leads 34011 to 34011.

The message (consisting, for instance, of 128 characters) which is dumped on lead 34211 is routed to shift register 28811 for the second time by an electornic commutator 346 (to be described later), the latter also being connected to the other seven shift registers (not shown) so that the intelligence on leads 34211 to 342k can be divided between the eight message channels on a time sharing basis. Shift register operations going into and out of the memory system 320 are of the parallel type so as to simplify the memory system circuitry. Specifically, intelligence is stored in each memory location by characters (eight bits) and not by individual bits. This requires that eight bits (a full character) are shifted simultaneously in parallel into the memory system 320 on leads 36411, 36611, 36811, 37011, 37211, 374a, 37611 and 37811 and at a later time to simultaneously remove eight informational bits (one character) from the memory system on leads 40211, 40411, 40611, 40811, 41011, 41211, 41411, and 41611. Accordingly, the eight outputs of commutator 346 (upon which eight bits simultaneously appear Ifrom the memory system 320) are connected to flip-ops 29011, 29211, 29411, 29611, 29811, 30011, 30211 and 30411 by leads 40211, 40411, 40611, 40811, 41011, 41211, 41411 Vand 41611. Shift register 28811 is used for the second time to translate eight character -bits supplied in parallel fashion into serial arrangement on output lines 347a, 34811 of shift register 28811, lead 34711 being grounded.

The dumped message informational bits on lead 34811 are conducted to an electronic switch 350 which s controlled by an address system (to be described later), the latter being yresponsive to the information in the second prefatory character of the message on incoming message line 1011. Specifically, electronic switch 350 controls the routing of the message from incoming line 1011 to one of the output lines 1211 to 12h and optionally with carbon copy to another line according to the coding of the second prefatory character, provided that such one or two outgoing message line or lines is/are available and not busy.

For transferring accumulated bits in simultaneous parallel fashion into memory system 320 after eight bits (corresponding to one character) are shifted into register 22811, advance character transitions are generated every eighth bit by three frequency dividers, 351, 352 and 353 connected in serial relationship, each dividing its input transitions or frequency by one half. The input to the first frequency divider 351 is connected to lead 306 which has impressed thereon the shift pulses corresponding to each message bit. The output of frequency divider 351 is connected to the input of frequency divider 352 by a lead 354 and the output of frequency divider 352 is connected to the input of frequency divider 353 by a lead 355. While the period of signals generated on lead 36011 connected to 354 is equal to four bits, its positive going transitions occur at a rate of eight bits or one character. Accordingly, an advance character transition every eighth bit is generated on output lead 356. A delay multivibrator 357 which is responsive to positive transitions is connected at its input side to lead 356 for providing advance character pulses on lead 36011 every eight message bits. Lead 36011 is connected to a load/unload funnel 370 (to be described later) so that after any one of the eight shift registers, such as 28811 (associated with line 1011) is filled, its bit information is simultaneously transferred in a parallel fashion to the input of commutator 338 on output leads 36411, 36611, 36811, 37011, 37211,

13 374:1, 376:1 and 378:1 of ip-flop 290:1 to 304:1, by the advance character pulses appearing every eighth bit on line 360:1.

As stated hereinbefore, the message bits on the output lines 340:1 to 340k of commutator 338 correspond to the message bits on all of the incoming lines :1 to 10h on a time sharing basis. Therefore, it is necessary to have a word locator funne 400 to 1route the message bits on lines 340:1 to 340k to its proper location in one of the memory sections 322 to 336. Such word locator funnel will be described later.

There will now be described a character counter which is necessary to determine when any one of the memory system sections 322 to 336 is filled and ready for dumping as well as to isolate the information in the second prefatory character which contains the instruction of which output lines 12:1 to 12h is to receive incoming message on line 10:1 and whether another preselected line is to receive a carbon copy. The character counter comprises frequency dividers 449, 450, 452, 453, 454, '456, 458 and 460 connected in series, each frequency divider reducing the frequency on its input by one-half. The input to the rst frequency divider 449 is connected to lead 356 energized by the output of frequency divider 353, the latter providing pulses every fourth bit of the message on the incoming line 10:1. Accordingly, the output of frequency divider 449 on lead 451 has generated thereon pulses corresponding to every one character while the signals on output leads 462 and 466 of the second frequency divider 450 and the last frequency divider 460 have pulses corresponding to every -2 and 128 characters, respectively. However, each message (according to the assumption previously made) has 128 message characters preceded by two prefatory characters and hence 130 characters have to be counted before a dump signal can be generated. As each of the memory sections 322 to 336 has a capacity for storing 12:8 characters, the two prefatory characters are erased and replaced by the 127th and 128th character.

Three conditions must be satis-fied before a dump signal is to be generated: ('l) 130 characters must be counted going into one of the memory sections 32-2 to 336; (2) the selected one of the outgoing lines 12:1 to 12h must be available (not busy) and (3) if a carbon copy of the message is to be simultaneously transmitted on a preselected one of the seven other outgoing lines (according, for instance, to the coding in the seventh bit of the second prefatory character), then such carbon copy line must also be available (not busy). An NAND gate 470:1 is provided to generate a dump signal when such conditions are satisfied. The output of frequency divider 460 on lead 466 is connected to one input of NAND gate 470:1. Another input to gate 470:1 is connected to the output of frequency divider 450 by lead 462. Condition (l) will be determined when simultaneous signals appear on leads 466 and 462 to signify a count of 130 characters. The third input to gate 470:1 on lead 472:1 will have a signal generated thereon (to be explained later) when conditions (2) and (3) are satisfied for generating a dump signal at the output side of NAND gate 470:1 on lead 287. Since lead 287 is also connected to one input of gates 284 (standard 600 Fieldata output code timing generator) and gate 286 (standard output 100 Baudot code timing generator), such standard pulse generators will be activated by the dump signal from gate 470:1.

As stated hereinbefore, only the second prefatory character of an entire message has the desired output line address information as well -as whether a preselected one of the outgoing lines will also have a carbon copy. For isolating and storing the second prefatory character information, ip-ops 480:1, 482:1, 484:1, 486:1 have their inputs connected to outputs of flip-flops 294:1, 296:1, 298:1 and 302:1 (corresponding to the third, fourth, fth and seventh bit) by leads 488, 490, 492, and 494, respectively. Normally, ip-fiops 480:1, 482:1, 484:1V and 486:1 are inhibited until an enabling pulse appears on a lead 496 connected to another input to each of such flip-flops. An enabling pulse should appear on lead 496 only after the complete second prefatory character appears in flip-Hops 294:1, 296:1, 298:1 and 302:1 of shift register 288:1 so as to isolate and store the second prefatory character information. Actually, the enabling pulse on line 496 is generated at the time when all eight bits are shifted into register 288:1. For this purpose, an NAND gate 500 has its six inputs connected to lead 462, the inverted output 4 of divider 452, the inverted output 8 of divider 453, the inverted output 16 of divider 454, the inverted output E of divider 458, and the inverted output '1% of divider 460, respectively. Accordingly, the signal on output lead 502 of gate 500 has a single pulse occurring only vfor the entire interval of the second prefatory character of the entire message on incoming line 10:1. However, to generate an enabling pulse on line 496 at the correct time, the signal on line 502 is gated with the advance character pulse on lead 360:1 through an NAND gate 504 and the output of gate 504 is connected to lead 496. Accordingly, flip-flops 480:1, 482:1, 484:1 and 486:1 are enabled to receive and store only the second prefatory character information on incoming line 10:1.

The output of flip-flops 480:1, 482:1, 484:1 (the output going line address information) appears on leads 507:1, 508:1 and 510:1 while the information YES (l) or NO (0) on output lead 512:1 from Hip-flop 486:1 signifies whether or not a carbon copy is also to be sent on a manually selected one of the other output lines 12:1 to 12h.

As explained hereinbefore, one (only) of the standard outgoing message bit generators 284 Baudot) or 286 (600 Fieldata) which is enabled by a signal level of one (only) of the flip-flops 96 to 104 or 150 to 158 is activated `by the dump signal on lead 287, such enabling signal level established during lill mode being sustained during the subsequent dump mode. The standard outgoing bit rate (100 Baudot or 600 Fieldata) on common lead 288 is connected to a second input of OR gate 317 so that shift register 288:1 when receiving stored character bits from memory system 320 is shifted at a desired bit rate by the signal on lead 306 connected to the output of gate 317.

As stated hereinbefore, the routing of the dumped message information is controlled by electronic switch 350 which will now be detailed in FIG. 9. In FIG. 9, the third, fourth, and fifth informational bit in the second prefatory character appearing on leads 507:1, 508:1 and 510:1 of FIG. 8 are connected to the input side of a Binary Number to Octal Number Encoder 514:1, for instance, Model OD-SO as manufactured and supplied by Computer Control Corp., Framingham, Mass. Encoders for two of the other seven channels are shown as 51417 and 514k with input leads 507b to 51011 and 507ky to 510k, respectively. The eight output leads of encoder 514:1 are connected to eight terminals 516, 518, 520, 522, 524, 526, 528, and 530 by leads 532:1, 534:1, 536:1, 538:1, 540:1, 542:1, 544:1 and 546:1, respectively. All of the terminals 516 to 530 are connected to lead 348:1 which is the message output lead from shift register 288:1 containing bit information for 128 characters in serial form. Since encoder 514:1 inhibits all of the terminals 516 to 530 except the one corresponding to the -binary address information on leads 507:1, 508:1 and 510:1, only one of the leads 532:1, 534:1, 536:1, 538:1, 540:1, 542:1, 544:1 or 546:1 connected to terminals 516, 518, 520, 522, 524, 526, 528 and 530, respectively, will conduct the signals on lead 348:1 to the right hand portion of FIG. 9. For this disclosure, an assumption will be made that the message on incoming line 10:1 is to be routed to the outgoing line 12b and hence the third, fourth and fifth lbits of the second prefatory character will be 0, l, 0. Accordingly, when the dump signal is generated on lead 472:1 (to be explained later) the dumped message on lead 348:1 will appear only on lead 1 5 534:1. It is to be understood that leads from the other seven encoders 514b to 514k corresponding to leads 532:1 to 546:1 for 514:1 will be designated with the same number but with a different suhx b to h for channels connected to incoming lines 12b and 12h.

FIG. 9 also illustrates eight similar OR gates 570:1, 570b, 570C, 570:1', 570e, 570f, 570g and 570k, each having nine inputs. Outgoing message lines 12:1 to 1211 are c-onnected to the output sides of gates 570:1 to 57011, respectively.

Each one of the first eight inputs to gate 570:1 is connected respectively to the first output lead 532:1, 532b, or 532k of encoders 514:1, 514b, 514k. In like manner, each of the first eight inputs to second OR gate 570b is connected respectively to the Second output lead 534:1 534b, or 534k. Also, each of the first eight inputs to gates 570:` to 570/1 is connected respectively to each of the third to eighth output terminals of encoders 514:1 to 514k. The ninth input terminal of each of the gates 570:1 to 570/1 is connected to terminals 580:1 to 58011 of the first level of a two level ganged switch 582 by leads 584:1, 584b, 584k, respectively. Ganged switch 582 is manually prepositioned according to which of the outgoing lines 12:1 to 12h is to receive a carbon copy. As shown in FIG. 9, the armature 586 is positioned in contact with contact 580:1 to signify that line 12:1 is to receive the carbon copy when the incoming message on line 10:1 is routed to outgoing line 12b (assumption made earlier in this disclosure).

Eight NAND gates 590:1, 590b, 590k are connected at their output sides to the armature 586 of the first level of ganged switch 582 by a lead 592. The two inputs to NAND gate 590:1 are connected to lead 512:1 and 348:1, respectively. In similar fashion, the two inputs of gates 590b to 590k are connected to the leads y510b `S10/1 and 548b 548k inthe second to eighth channels (associated with incoming lines 12b to 12h) corresponding to leads 510:1 and 548:1 of the channel illustrated in FIG. la.

According to the circuitry in FIG. 9, the message dumped upon lead 348:1 is routed only to outgoing line 12b as determined by the coded signals on lead 510:1 which appear in the second prefatory character on incoming line 10:1. Also, when the signal on lead 512:1 is a YES or a 1, to open gate 590:17 the message appearing on line 348:1 is passed by gate 590C to lead 592, armature 586, contact 580:1, lead 584:1, OR gate 570:1 and output line 12:1 which has been chosen (assumed) to receive the carbon copy. It will be noted that according to the circuitry of FIG. 9, any message in any of the other seven channels will also have a carbon copy sent to outgoing line 12:1 according to the one predetermined setting of ganged switch 582.

In explaining the message routing according to FIG. 9, it was assumed that the message was dumped upon lead 348:1. However, the message signals from memory systern 320 cannot be dumped upon lead 348:1 unless both the outgoing message line (12b as assumed) and the carbon copy lines (12:1 as assumed) are available, that is to say, not busy. It will now be explained in conjunction with FIG. 16 how the message consisting of 128 characters is not dumped upon line 348:1 unless both lines 12:1 and 12b are available.

FIG. 16 illustrates an Outgoing Line Request Funnel which determines whether (A) the desired outgoing line is available if no carbon copy is to be simultaneously dispatched therewith or (B) both the desired outgoing line and the carbon copy line are available when a carbon copy is to be simultaneously dispatched. Very importantly, such funnel as shown in FIG. 16 operates on a time sharing basis to reduce the number of cornponents for handling the eight channels. Associated with the equipment of FIG. 16 is the master clock oscillator 62 (see FIG. 1:1) which is common to all eight channels and four frequency dividers 680, 682, 684 and 686 which are connected in series to the output of 62 by a lead 688, divider 682 being connected to the output of divider 680 by a lead 690, divider 684 being connected to the output of divider 682 by a lead 692, divider 686 being connected to the output of divider 684 by a lead 694. A Binary Number to Octal Number Encoder 696 has its three inputs connected to leads 692, 694 and 698, the latter being connected to the output of divider 686. As established hereinbefore, when the master clock oscillator frequency is divided by 16 with 4four serially connected frequency dividers (such as 680, 682, 684 and 686), the resulting frequency is 93 microseconds or one clock count. Therefore, the sequential binary number inputs to encoder 696 on leads 692, 694 and 698 result in the sequential uninhibiting of each of the eight outputs 499a 499b, 499e, 499:1', 499e, 4991*, 499g and 49911 of encoder 696 every one clock count, the uninhibiting pulses appearing on each of the eight output lines 499:1 to 49911 at time spaced intervals of one-eighth of a clock count. Encoder 696 and its eight outputs 499:1 to 499k will be employed as common equipment to all eight channels and will be designated the channel access counter.

In FIG. 16, there is illustrated only the four second prefatory character flip-flops 480:: to 486:1 and 480k to 486h associated with the first and last channel and it will be assumed that the corresponding ip-fiops and associated gates are present although not shown. Each flip-flops is connected to one input of a NAND gate, for instance: 480:1 is connected to one input of a gate 950:1 by a lead 951:1; 480k is connected to one input of a gate 952k by a lead 953k; 486:1 is connected to one input of a gate 954:1. by a lead 955:1, 486h is connected to one input of a gate 956k by a lead 957k, etc. Channel/encoder 696 of FIG. 1:1 is also shown in FIG. 16 with its 499:1 output lead connected to the second inputs of the four gates (including 950:1 and 954:1) associated with channel 1 (incoming line 10:1) and its 4991: output lead connected to the second inputs of the four gates (including 952k and 956k) associated with channel 8 (incoming line 10h). The other six outputs 499b to 499g of 696 are similarly connected to 24 gates (not shown). The output of the eight gates, including 950:1 and 952k, associated with the first flip-Hop, including 950:1 and 952k, of all eight channels are connected to a common lead 958. Similarly, common leads 959 and 960 are connected to the second and third gates, respectively, of all eight channels. Also, a common lead 961 is connected to all the fourth gates, including 954k and 95611, of all eight channels.

A Binary Number to Octal Number Encoder 600 (similar to 514:1 to 514k and 696) is common to all eight channels and has its three inputs connected to leads 958, 959 and 960. Accordingly, output leads 602:1 to 616:1 are sequentially (for a period of one-eighth of a count) uninhibited according to the address information of the first three bits in the second prefatory character on all eight incoming lines 10:1 to 10h.

Associated with each output lead 602:1l to 616:1 of encoder 600 is a NAND gate, such as 620:1, 620b and 62011 in FIG. 16, the other five gates being omitted from the drawing `for simplicitys sake.

The inputs to gates 620:1 are connected to the first output terminal of encoder 600:1 and the output of ipflop 640:1 on lead 642:1, respectively. In similar fashion, one input to gate 620b is connected to output 604a of encoder 600:1 and the other input to gate 620b is connected to the output of Hip-flop 64011. Also, one input of gate 620k is connected to the eighth output 616:1 of encoder 600:1 while the other input of gate 620k is connected to Hip-op 640k. The output of all eight gates (of the group consisting of 620:1 to 620k) are connected at their output sides to an inverter 636 by a lead 638.

For determining whether each of the outgoing lines 12:1 to 12h is busy or available, flip-flops 640a to 640k are connected individually to outgoing lines 12:1 to 12h (see FIG. 9). The output of flip-flops 640:1 to 640k as- 

